Jason Cong

Jason Cong
Jason Cong
An haife shi	1963 (shekaru 62-63) Beijing ;
Kasancewa ɗan ƙasa	Amurka
Ilimi	Jami'ar Peking (digiri na BS a kimiyyar kwamfuta), Jami'ar Illinois a Urbana-Champaign (PhD)
Ayyuka	masanin kimiyyar kwamfuta, mai bincike, malami, da kuma dan kasuwa
Kyaututtuka	2022 IEEE Robert N. Noyce Medal, 2024 Phil Kaufman Award

Jason Cong
Rayuwa
Haihuwa	1963 (62/63 shekaru)
Karatu
Makaranta	Peking University (en) ; University of Illinois Urbana–Champaign (en)
Thesis director	Chung Laung Liu (en)
Dalibin daktanci	Tianming Kong (mul) ; Chin-Chih Chang (mul) ; Songjie Xu (mul) ; Jie Fang (mul) ; Zhigang Pan (mul) ; Sung Kyu Lim (mul) ; Lei He (mul) ; Chang Wu (mul) ; Yean-Yow Hwang (mul) ; Cheng-Kok Koh (mul) ; Patrick H. Madden (mul) ; Yuzheng Ding (mul) ; Xin Yuan (mul) ; Michail Romesis (mul) ; Michael Gang Chen (mul) ; Ashok Jagannathan (mul) ; Deming Chen (mul) ; Kenton Nang Keung Sze (mul) ; Yan Zhang (mul) ; Min Xie (mul) ; Yizhou Joey Lin (mul) ; Yiping Fan (mul) ; Zhiru Zhang (mul) ; Guoling Han (mul) ; Wei Jiang (mul) ; Kirrill Minkovich (mul) ; Guojie Luo (mul) ; Peipei Zhou (mul)
Sana'a
Sana'a	computer scientist (en)
Employers	University of California, Los Angeles (en)
Kyaututtuka	gani ACM Fellow (2008) ; IEEE Fellow ; IEEE Robert N. Noyce Medal (2022) ;
Mamba	The Institute of Electrical and Electronics Engineers, Incorporated (mul) ; ACM (mul)

Jingsheng Jason Cong (Chinese; an haife shi a 1963 a Beijing) masanin kimiyyar kwamfuta ne na kasar Sin, malami, kuma ɗan kasuwa.

Ilimi da aiki

Ya sami digiri na BS a kimiyyar kwamfuta daga Jami'ar Peking a 1985, digiri na MS da Ph.D. a kimiyyyar kwamfyutoci daga Jami'an Illinois a Urbana-Champaign a 1987 da 1990, bi da bi. Ya kasance a cikin bangaren koyarwa a Sashen Kimiyya na Kwamfuta a Jami'ar California, Los Angeles (UCLA) tun 1990. A halin yanzu, shi Farfesa ne mai daraja, Shugaban Volgenau na Kwarewar Injiniya, da kuma daraktocin Cibiyar Nazarin Yanki (CDSC), VLSI Architecture, Synthesis, da Fasaha (VAST) Laboratory.

Bincike da tasiri

Cong ya ba da gudummawa mai mahimmanci ga fasahar kira ta FPGA. Sakamakon sa a farkon shekarun 1990s a kan taswirar zurfi (FlowMap) don binciken-table-based FPGAs ^[1] shine babban tushe na duk kayan aikin kira na FPGA da aka yi amfani da su a yau. Wannan, tare da ayyukan da suka biyo baya a kan ƙididdigar ƙididdiga da daidaitawar Boolean hanyoyin da suka danganci taswirar FPGA, sun haifar da kamfani mai cin nasara Aplus Design Technologies (1998-2003) wanda Cong ya kafa.^[2] Aplus ta haɓaka kayan aikin kimanta gine-ginen FPGA na farko da ke samuwa a kasuwa da kayan aikin kira na jiki, waɗanda yawancin kamfanonin FPGA suka tsara kuma suka rarraba ga dubban masu zanen FPGA a duk duniya. Magma Design Automation ta sayi Aplus a cikin 2003, wanda yanzu yana cikin Synopsys.

Binciken Cong ya kuma yi tasiri sosai a kan kira mai girma (HLS) don hadadden da'irori. Binciken shekaru goma da ƙungiyarsa ta yi a cikin 2000s ya haifar da wani UCLA spin-off, AutoESL Design Automation (2006-2011), wanda Cong ya kafa. AutoESL ta haɓaka kayan aikin HLS da aka fi amfani da su don FPGAs ^[3] kuma Xilinx ta samo shi a cikin 2011. Kayan aikin HLS daga AutoESL (wanda aka sake masa suna Vivado HLS bayan sayen Xilinx) yana bawa masu zanen FPGA damar amfani da harsunan shirye-shiryen software na C / C ++ maimakon harsunan bayanin kayan aiki don ƙirar FPGA da aiwatarwa.^[4]

A shekara ta 2009, Cong ya jagoranci ƙungiyar mambobi goma sha biyu daga UCLA, Rice, Ohio-State, da UC Santa Barbara kuma ya lashe kyautar NSF Expeditions in Computing Award a kan Kayan Kayan Kimiyyar Kayan Kundin Kayan Kiman (CDSC). ^[5]

Binciken Cong game da ƙirar haɗin kai don haɗin kai yana taka muhimmiyar rawa wajen shawo kan ƙalubalen rufewa na lokaci a cikin ƙirar submicron mai zurfi a cikin 1990s. Ayyukansa a kan shirin haɗin gwiwar VLSI, kira, da ingantaccen layout da kuma daidaitaccen tsarin bincike mai yawa an saka su a cikin ainihin kayan aikin kira na zahiri wanda masana'antar EDA ta kirkira. Misali mafi sanannun tallafin masana'antu shine Magma_Design_Automation" id="mwPw" rel="mw:WikiLink" title="Magma Design Automation">Magma Design Automation, wanda aka kafa a cikin 1997 da nufin cimma rufewar lokaci ta hanyar kira ta jiki. Cong ya yi aiki a kwamitin ba da shawara na fasaha tun lokacin da aka kafa shi har zuwa IPO, sannan daga baya a matsayin Babban Mai ba da shawara kan Fasaha daga 2003 zuwa 2008. Synopsys ne suka sayi Magma a shekarar 2012.

Kyaututtuka da aka zaɓa

2022 IEEE Robert N. Noyce Medal don "babban gudummawa ga ƙirar lantarki da hanyoyin ƙirar FPGA". ^[6]

2024 Phil Kaufman Award don gudummawa ta asali ga fasahar sarrafa kansa ta FPGA.

2024 ACM Chuck Thacker Breakthrough Award don "babban gudummawa ga ƙira da sarrafa kansa na tsarin shirye-shiryen filin da ƙididdigar da za a iya keɓancewa".^[7]

Ayyukan Cong a kan FlowMap sun sami lambar yabo ta ACM / IEEE A. Richard Newton Technical Impact Award a cikin Electronic Design Automation "don aikin farko a kan taswirar fasaha don FPGA wanda ya yi tasiri sosai ga al'ummar bincike da masana'antu na FPGA", kuma shine na farko da aka shigar da shi cikin FPGA da Reconfigurable Computing Hall of Fame ta ACM TCFPGA.

An zabi Cong a matsayin IEEE Fellow a cikin 2000 "don gudummawa mai mahimmanci a cikin ƙirar taimakon kwamfuta na haɗin kai, musamman a cikin ƙira ta jiki, inganta haɗin kai, da kuma kira na FPGAs", da ACM Fellow a 2008 "don gud gudummawa ga ƙirar sarrafa kansa ta lantarki".^[8]

Ya sami lambar yabo ta 2010 IEEE Circuits and System (CAS) Society Technical Achievement Award ^[9] "Don gudummawa mai mahimmanci ga ƙirar lantarki ta atomatik, musamman a cikin kira na FPGA, inganta haɗin haɗin VLSI, da ƙirar ƙirar jiki", da kuma lambar yabo ta 2016 IEEE Computer Society Technical Achievement Award "Don saita tushe na algorithmic don ƙaddamar da ƙofar filin da za a iya tsarawa". Shi kadai ne wanda ya sami lambar yabo ta fasaha daga duka IEEE Circuits and Systems Society da Computer Society.

A watan Fabrairun 2017, an zabi Cong a matsayin memba a Kwalejin Injiniya ta Kasa . An zabe shi memba na kasashen waje na Kwalejin Injiniya ta kasar Sin a shekarar 2019. ^[10]

A cikin 2020, an zabe shi ya zama ɗan'uwan Kwalejin Inventors ta Kasa, ^[11] kuma a cikin 2024, an zabe shi a matsayin memba na Kwalejin Fasaha da Kimiyya ta Amurka. ^[12]

Manazarta

↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong and Y. Y. Hwang, "Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation", Proceedings of the 1998 Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1998, pp. 27-34. doi:10.1145/275107.275116.
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)
↑ J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.
↑ J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)

Haɗin waje

Jason Congwallafe-wallafen da aka jera taMasanin Google

[1] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[2] J. Cong and Y. Y. Hwang, "Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation", Proceedings of the 1998 Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1998, pp. 27-34. doi:10.1145/275107.275116.

[3] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[4] J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)

[5] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[6] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[7] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[8] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[9] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[10] J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)

[11] J. Cong and Y. Ding, (1994) "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on Computer-Aided Design. 13 (1). pp. 1-12. doi:10.1109/43.273754}.

[12] J. Cong, C. Wu, and Y. Ding, "Cut Ranking and Pruning: Enabling A General and Efficient FPGA Mapping Solution," Proceedings of the Int'l Symposium on Field-Programmable Gate-Arrays, Monterey, California, February 1999, pp. 29-35. (Selected for FPGA20: the most significant contributions in the FPGA Symposium from 1992 – 2001)

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